1. Field of the Invention
The present invention relates to clock and data recovery (CDR) systems, and, in particular, to correction of DC offset in a CDR system.
2. Background of the Invention
In many applications, including digital communications, clock and data recovery (CDR) systems are employed to recover correct timing (frequency and phase) of an input data stream, which timing is then employed to sample the input data stream to recover the user data for decoding. A serializer and de-serializer (SerDes) device is commonly used in high speed communications to convert data between serial and parallel interfaces in each transmit/receive direction.
SerDes devices often employ an encoding scheme that supports DC-balance, provides framing, and guarantees signal transitions. Guaranteed transitions allow a receiver to extract the embedded clock signal (clock data recovery, or CDR), while control codes allow framing, typically on the start of a data packet. This encoding scheme also improves error detection with running disparity, providing separation of data bits from control bits, and permits derivation of byte and word synchronization.
Mismatches in the analog symmetric path give rise to DC offset in the input signal, degrading system performance of a CDR system. Usually, calibration for DC offset is performed prior to operation with live traffic (a user data stream). DC offset calibration is performed by shorting the device input and applying an opposite DC offset to equalize the built-in offset. However, DC offset is a function of gain, and during operation with a user data stream, the DC offset varies as a function of gain.